MSc Karmakar

1. The Zoom ADC: An Evolving Architecture
   Eland, Efraïm; Mehrotra, Shubham; Karmakar, Shoubhik; van Veldhoven, Robert; Makinwa, Kofi A. A.;
   Harpe, Pieter; Baschirotto, Andrea; Makinwa, Kofi A.A. (Ed.);
   Cham: Springer International Publishing, , pp. 179--201, 2023. DOI: 10.1007/978-3-031-28912-5_10
   
   Abstract: ...

   Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator ($\Delta$$\Sigma$M) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This chapter presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 $\mu$m technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only hundreds of $\mu$Ws.

2. A −91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping
   Karmakar, Shoubhik; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen;
   IEEE Journal of Solid-State Circuits,
   Volume 57, Issue 12, pp. 3726-3735, 2022. DOI: 10.1109/JSSC.2022.3207386

3. A -91 dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping
   Karmakar, Shoubhik; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen;
   In 2022 IEEE International Solid-State Circuits Conference (ISSCC),
   pp. 1-3, 2022. DOI: 10.1109/ISSCC42614.2022.9731736

4. A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC
   Mehrotra, Shubham; Eland, Efraïm; Karmakar, Shoubhik; Liu, Angqi; Gönen, Burak; Bolatkale, Muhammed; Van Veldhoven, Robert; Makinwa, Kofi A.A.;
   In ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC),
   pp. 253-256, 2022. DOI: 10.1109/ESSCIRC55480.2022.9911295

5. A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
   E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
   IEEE Journal of Solid-State Circuits,
   Volume 56, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
   
   Abstract: ...

   This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

6. A High-Linearity and Low-EMI Multilevel Class-D Amplifier
   Zhang, Huajun; Karmakar, Shoubhik; Breems, Lucien J.; Sandifort, Quino; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen;
   IEEE Journal of Solid-State Circuits,
   Volume 56, Issue 4, pp. 1176-1185, 2021. DOI: 10.1109/JSSC.2020.3043815

7. A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers
   Rooijers, Thije; Karmakar, Shoubhik; Kusuda, Yoshinori; Huijsing, Johan H.; Makinwa, Kofi A. A.;
   IEEE Journal of Solid-State Circuits,
   Volume 56, Issue 12, pp. 3583-3592, 2021. DOI: 10.1109/JSSC.2021.3107350

8. A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
   E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
   IEEE Journal of Solid-State Circuits,
   Volume 56, Issue 4, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
   
   Abstract: ...

   This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

9. A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMD
   T. Rooijers; S. Karmakar; Y. Kusuda; J. H. Huijsing; K. A. A. Makinwa;
   In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
   February 2021. DOI: 10.1109/ISSCC42613.2021.9365790

10. A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMD
    T. Rooijers; S. Karmakar; Y. Kusuda; J. H. Huijsing; K. A. A. Makinwa;
    In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 438-440, February 2021. DOI: 10.1109/ISSCC42613.2021.9365790

11. A 28-W, −102.2-dB THD+N Class-D Amplifier Using a Hybrid ΔΣM-PWM Scheme
    Karmakar, Shoubhik; Zhang, Huajun; van Veldhoven, Robert; Breems, Lucien J.; Berkhout, Marco; Fan, Qinwen; Makinwa, Kofi A. A.;
    IEEE Journal of Solid-State Circuits,
    Volume 55, Issue 12, pp. 3146-3156, 2020. DOI: 10.1109/JSSC.2020.3023874

12. A 440μW, 109.8dB DR, 106.5dB SNDR Discrete-Time Zoom ADC with a 20kHz BW
    E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. Makinwa;
    In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
    June 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856.

13. A 440μW, 109.8dB DR, 106.5dB SNDR Discrete-Time Zoom ADC with a 20kHz BW
    Eland, Efraïm; Karmakar, Shoubhik; Gönen, Burak; van Veldhoven, Robert; Makinwa, Kofi;
    In 2020 IEEE Symposium on VLSI Circuits,
    pp. 1-2, 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856

14. A −107.8 dB THD+N Low-EMI Multi-Level Class-D Audio Amplifier
    Zhang, Huajun; Karmakar, Shoubhik; Breems, Lucien; Sandifort, Quino; Berkhout, Marco; Makinwa, Kofi; Fan, Qinwen;
    In 2020 IEEE Symposium on VLSI Circuits,
    pp. 1-2, 2020. DOI: 10.1109/VLSICircuits18222.2020.9162793

15. A 28W -108.9dB/-102.2dB THD/THD+N Hybrid $\Delta\Sigma-$-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission
    Karmakar, Shoubhik; Zhang, Huajun; Van Veldhoven, Robert; Breems, Lucien; Berkhout, Marco; Fan, Qinwen; Makinwa, Kofi A.A.;
    In 2020 IEEE International Solid-State Circuits Conference - (ISSCC),
    pp. 350-352, 2020. DOI: 10.1109/ISSCC19947.2020.9063001

16. A Low Power Continuous-Time Zoom ADC for Audio Applications
    B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 55, pp. 1023-1031, 12 2019. DOI: 10.1109/JSSC.2019.2959480
    
    Abstract: ...

    This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.

17. A Low Power Continuous-Time Zoom ADC for Audio Applications
    B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 55, Issue 4, pp. 1023-1031, 12 2019. DOI: 10.1109/JSSC.2019.2959480
    
    Abstract: ...

    This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.

18. A Low Power Continuous-Time Zoom ADC for Audio Applications
    B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
    In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
    6 2019. DOI: 10.23919/VLSIC.2019.8778021

19. A Low Power Continuous-Time Zoom ADC for Audio Applications
    B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
    In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
    pp. C224-C225, 6 2019. DOI: 10.23919/VLSIC.2019.8778021

20. A 280μW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
    S. Karmakar; B. Gonen; F. Sebstiano; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 12, pp. 3497-3507, 12 2018. DOI: 10.1109/JSSC.2018.2865466
    
    Abstract: ...

    This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW . This results in a Schreier figure of merit (FoM) of 185.8 dB.

21. A 280μW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
    S. Karmakar; B. Gonen; F. Sebstiano; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 12, pp. 3497-3507, 12 2018. DOI: 10.1109/JSSC.2018.2865466
    
    Abstract: ...

    This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW . This results in a Schreier figure of merit (FoM) of 185.8 dB.

22. A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BWA 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
    S. Karmakar; B. Gònen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
    In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 238-240, 2 2018. DOI: 10.1109/ISSCC.2018.8310272

23. A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BWA 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
    S. Karmakar; B. Gònen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
    In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 238-240, 2 2018. DOI: 10.1109/ISSCC.2018.8310272

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